Fin field effect transistors (FinFETs) are non-planar, multi-gate transistors having “fins” that perpendicularly extend from the gate and form the source and the drain of the transistor. FIG. 1A is a perspective view of a FinFET 100. As shown in FIG. 1A, FinFET 100 includes a vertical silicon fin 104 extending above the substrate 102. Fin 104 is used to form the source and drain 106 regions and a channel therebetween (not shown). A vertical gate 108 intersects the channel region of fin 104. An oxide layer 110 and insulating sidewall spacers 112, 114 are respectively formed on the source and drain regions 106 and the vertical gate 108. The ends of fin 104 are doped to form the source and drain 106 to make fin 104 conductive.
Multiple FinFETs may be coupled to one another to provide an integrated circuit device. A conductive layer may be formed over the fins to provide a local interconnect between adjacent FinFETs. The use of local interconnects enables a higher packing density, which in turn reduces the required chip area for an integrated circuit. However, the formation of the slot contact of the local interconnects increases the parasitic fringe capacitance, which significantly degrades the circuit speed.
Accordingly, an improved FinFET and local interconnect structure are desirable.